The present invention relates to semiconductor memory devices. More particularly, the present invention relates to variable resistance memories and read methods thereof.
There have been increased demands for semiconductor memory devices capable of being accessed randomly and realizing high integration and large volume. Such semiconductor memory devices may include a flash memory device which may be used in portable electronic devices. Further, there have been developed semiconductor memory devices using non-volatile materials instead of capacitors in DRAM. For example, such semiconductor memory devices may include Ferroelectric RAM (FRAM) using ferroelectric capacitors, Magnetic RAM (MRAM) using Tunneling Magneto-Resistive (TMR) films, phase change memory using chalcogenide alloys, and the like. In particular, the phase change memory is a non-volatile memory device and is made via a relatively simple fabrication process. Further, it is possible to realize a large-capacity memory in a low cost with the phase change memory.
A phase change memory cell may use a material which is capable of being changed between structured states indicating different electric read characteristics. For example, there are known memory devices made of chalcogenide material including germanium (Ge), antimony (Sb), and tellurium (Te) (hereinafter, referring to as GST material). The GST material may have an amorphous state indicating a relatively high resistivity and a crystalline state indicating a relatively low resistivity. That is, data corresponding to an amorphous or crystalline state may be written in a phase change memory cell by heating a GST material. Heating duration and magnitude may be determined according to whether a GST material remains at an amorphous state or a crystalline state. High and low resistivities indicate written logic values 1 and 0, which is sensed by measuring a resistivity of the GST material. Accordingly, a phase change memory device is a type of variable-resistance memory device.
A memory cell of a phase change memory device includes a resistive element and a switching element. FIG. 1 shows a resistive element 10 of a phase change memory cell. The resistive element 10 may a variable resistance value according to an applied current I. Referring to a cross-sectional view of the resistive element 10, the resistive element 10 includes a top electrode 11, a phase change material 12, a contact plug 13, and a bottom electrode 14. The top electrode 11 is connected to a bit line, and the lower electrode 14 is connected between the contact plug 13 and an access transistor or diode (not shown). The contact plug 13 is formed of a conductive material (e.g., TiN) and is also called a heater plug. The phase change material 12 is provided between the top electrode 11 and the contact plug 13. A phase of the phase change material 12 may be changed according to amplitude, duration, and/or fall time of an applied current pulse. A phase of the phase change material corresponding to a set or reset may be determined according to an amorphous volume 15 as illustrated in FIG. 1. In general, an amorphous phase and a crystal phase correspond to a reset state and a set state, respectively. An amorphous volume is reduced as a phase is changed from an amorphous state to a crystal state. The phase change material 12 has a resistance which is changed according to a formed amorphous volume 15. That is, written data may be determined according to an amorphous volume 15 of the phase change material 12 formed according to different current pulses.
Unfortunately, the phase change material 12 may suffer threshold voltage recovery and resistance drift according to an elapsed time after it is programmed. This makes a sensing margin of the phase change memory reduced.
FIG. 2 is a graph showing threshold voltage recovery and resistance drift caused at a resistive element 10 in FIG. 1. Referring to FIG. 2, a horizontal axis indicates an elapsed time after a memory cell is programmed. A vertical axis indicates a resistance value of a memory cell. A resistance of a resistive element 10 may be changed according to an elapsed time due to various causes. Such causes may include threshold voltage recovery and resistance drift.
A threshold voltage recovery problem may arise when a threshold voltage is not stabilized immediately after a write pulse is supplied to the resistive element 10. That is, electrons of high concentration may be captured at a donor-like trap (C3+) layer in an energy band of a memory cell which is programmed to have a reset state according to applying of a write pulse to the resistive element 10. Accordingly, before the electrons of high concentration captured at the donor-like trap (C3+) layer are recombined, electron concentration of a conduction band may become high due to the captured electrons. If a sensing operation is conducted before the electrons of high concentration captured at the donor-like trap (C3+) layer are recombined, a reset resistance R_rst of the resistive element 10 becomes low. This means that it is not easy to secure a sensing margin. After a write pulse is applied as illustrated in FIG. 2, at an elapse interval ΔT1 of a time t0, a variation curve 26 of a reset resistance R_rst is sharply changed since the threshold voltage recovery acts as a dominant factor. Referring to an elapsed time t1, a distribution of the reset resistance R_rst shows a distribution chart 23. In this case, a distribution of a set resistance R_set shows a distribution chart 21. Accordingly, in order to provide a sufficient sensing margin SM1, a sensing operation has to be conducted after a write operation is conducted and then a sufficient time (e.g., 30 ns) elapses.
Together with the threshold voltage recovery, a resistance drift also causes reduction of a sensing margin. After a write pulse is applied, as illustrated in FIG. 2, a reset resistance R_rst of a resistance element 10 after an elapse of a time t0 is not maintained but increased according to an elapse after it is programmed. After a write pulse is applied, an average value of a reset resistance R_rst is changed after an elapse of a time t2. In a multi-level cell, this characteristic of the resistance element may reduce a sensing margin. Resistance variation according an elapse may act as a restriction factor to realize a multi-level phase change memory device.
Threshold voltage recovery and resistance drift characteristics of a phase change material are disclosed in papers, entitled “Electronic Switching in Phase-Change Memories” (A. Pirovano et al, IEEE Trans. Electron Devices, 51, 452 (2004)), “Low-Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials” (A. Pirovano et al, IEEE Trans. Electron Devices, 51, 1 (2004)), “Ovonic Unified Memory—A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications” (M. Gill et al, ISSCC, (2002)), and “Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memories” (D. Ielmini, IEEE Trans. Electron Devices, 54, 308 (2007)), the entirety of which is hereby incorporated by reference.
In order to provide added value of memory devices, it is desirable to provide high-speed write and read functions. In particular, a phase change memory device may necessitate a high access speed in order to support various services such as a random access memory such as DRAM, SSD, and a storage unit for a mobile apparatus. However, the above-described threshold voltage recovery and resistance drift characteristics of the phase change material may act as a restriction factor to perform a write and a read operation in a high speed. It may be difficult to perform a high-speed write operation without securing of a sufficient sensing margin in order to apply a scheme in which a write-verify read operation is conducted. This technical obstacle may prevent the use of the resistance element at a multi-level cell MLC.